Efficient Design of FFT Module Using Dual Edge Triggered Flip Flop and Clock Gating

Preyadharan R, Tamilselvan A

Abstract


>In this paper, an approach to develop Fast Fourier Transform (FFT) module is with the help of the architecture level and system level is proposed. OFDM is used in many communication systems such as high data rate mobile wireless communication. In the OFDM architecture, FFT is used to modulate the data where it is converted from time domain to frequency domain at the receiver and IFFT converts frequency domain to time domain at the transmitter. Both transforms are same; the only difference is the twiddle factors in each being the complex conjugate of one another. FFT is efficiently used to compute Discrete Fourier Transform (DFT) and its inverse. In this proposed system, FFT used in Orthogonal Frequency Division Multiplexing (OFDM) is realized using dual edge triggered flip flop (DETFF) instead of using single edge triggered flip flop traditionally in the architectural level and using the gated clocking for the input system in order to reduce the power consuming. Speed of processing is one of the important factors of the blocks in OFDM system. By using DETFF, it captures and propagate the data at both clock edges hence it is suitable for high data rate applications and also speed of FFT module can be increased. Power consuming in the design due to the clock dissipation by using the Clock Gating method to reduce the clock power. This proposed structure can modify the designs in both architectural structure and system level structure. 


Keywords


Computer Science; ASDF Journals; ASDF; ASDF International; Electronics; Communication Engineering; Communication; Engineering

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References


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